A Reference-Less Single-Loop Half-Rate Binary CDR

被引：34

作者：

Jalali, Mohammad Sadegh ^{[1
]}

Sheikholeslami, Ali ^{[1
]}

Kibune, Masaya ^{[2
]}

Tamura, Hirotaka ^{[2
]}

机构：

[1] Univ Toronto, Dept Elect & Comp Engn, Toronto, ON M5S 3G4, Canada

[2] Fujitsu Labs Ltd, Kawasaki, Kanagawa 2118588, Japan

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 2015年 / 50卷 / 09期

基金：

加拿大自然科学与工程研究理事会;

关键词：

Burst-mode CDR; clock and data recovery; cycle-slipping; frequency detection; gated VCO; DATA RECOVERY CIRCUIT; 10-GB/S CMOS CLOCK;

D O I：

10.1109/JSSC.2015.2429714

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper proposes a half-rate single-loop reference-less binary CDR that operates from 8.5 Gb/s to 12.1 Gb/s (36% capture range). The high capture range is made possible by adding a novel frequency detection mechanism which limits the magnitude of the phase error between the input data and the VCO clock. The proposed frequency detector produces three phases of the data, and feeds into the phase detector the data phase that minimizes the CDR phase error. This frequency detector, implemented within a 10 Gb/s CDR in Fujitsu's 65 nm CMOS, consumes 11 mW and improves the capture range by up to 6x when it is activated.

引用

页码：2037 / 2047

页数：11

共 50 条

[1] Referenceless single-loop CDR with a half-rate linear PD and frequency acquisition technique
Kim H.R.
Chun J.-H.
Chun, J.-H. (jhchun@skku.edu), 1600, John Wiley and Sons Inc (56): : 237 - 239
[2] Referenceless single-loop CDR with a half-rate linear PD and frequency acquisition technique
Kim, H. R.
Chun, J. -H.
ELECTRONICS LETTERS, 2020, 56 (05) : 237 - +
[3] A 7∼10.5-Gb/s Reference-Less Linear Half-rate CDR Circuit Using Automatic Band Selector
Hsu, Yi-En
Liu, Shen-Iuan
2023 INTERNATIONAL VLSI SYMPOSIUM ON TECHNOLOGY, SYSTEMS AND APPLICATIONS, VLSI-TSA/VLSI-DAT, 2023,
[4] A 10 Gb/s PAM4 receiver with reference-less half-rate Bang-Bang CDR in 180-nm CMOS
Liu, Jiaxin
Zhang, Yinhang
Yin, Chao
Yang, Xi
Zhan, Yongzheng
MICROELECTRONICS JOURNAL, 2025, 157
[5] A 0.8-to-6.5 Gb/s Continuous-Rate Reference-Less Digital CDR With Half-Rate Common-Mode Clock-Embedded Signaling
Lee, Kyongsu
Sim, Jae-Yoon
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2016, 63 (04) : 482 - 493
[6] A 6.5-12.5-Gb/s Half-Rate Single-Loop All-Digital Referenceless CDR in 28-nm CMOS
Yu, Changzhi
Sa, Euije
Jin, Soowan
Park, Himchan
Shin, Jongshin
Burm, Jinwook
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2020, 55 (10) : 2831 - 2841
[7] An 8-26 Gb/s Single Loop Reference-less CDR with Unrestricted Frequency Acquisition
Lee, Hyung-Wook
Ko, Kyeong-Min
Kang, Jin-Ku
18TH INTERNATIONAL SOC DESIGN CONFERENCE 2021 (ISOCC 2021), 2021, : 45 - 46
[8] A 14-Gb/s PAM4 Reference-Less Half-Baud-Rate CDR
Khiarak, M. Noormohammadi
Gosselin, B.
2022 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS 22), 2022, : 985 - 989
[9] A 0.5-to-2.5 Gb/s Reference-Less Half-Rate Digital CDR With Unlimited Frequency Acquisition Range and Improved Input Duty-Cycle Error Tolerance
Inti, Rajesh
Yin, Wenjing
Elshazly, Amr
Sasidhar, Naga
Hanumolu, Pavan Kumar
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2011, 46 (12) : 3150 - 3162
[10] A 10-Gb/s Dual-Loop Reference-less CDR with FD Controller
Kim, Sihan
Song, Changmin
Kim, Jinseok
Oh, Yonghun
Kim, Changwan
Jang, Young-Chan
2023 20TH INTERNATIONAL SOC DESIGN CONFERENCE, ISOCC, 2023, : 109 - 110

← 1 2 3 4 5 →