New constraint for Vth optimization for sub 32nm node CMOS gates scaling

被引：0
|
作者：
Morifuji, E [1 ]
Kapur, P [1 ]
Chao, AKA [1 ]
Nishi, Y [1 ]
机构：
[1] Stanford Univ, Dept Elect Engn, Ctr Integrated Syst, Stanford, CA 94305 USA
来源：
IEEE INTERNATIONAL ELECTRON DEVICES MEETING 2005, TECHNICAL DIGEST | 2005年
关键词：
D O I：
暂无
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
We show new constraint Of V-th scaling for logic blocks from inverter operation viewpoint. In lower V-th region, delay time in inverter chain saturates because of the loss in overdrive for the input of MOSFETs. This loss will dominate the inverter speed in scaled V-dd region and we propose a new relaxed scaling scenario. This accounts for the speed loss using a simplified model which adequately manifests the new phenomenon.
引用
收藏
页码：1049 / 1052
页数：4
相关论文
共 50 条
  • [41] Material Loss Impact on Device Performance for 32nm CMOS And Beyond
    Kirkpatrick, Brian K.
    Chambers, James J.
    Prins, Steven L.
    Riley, Deborah J.
    Wade Xiong, Weize
    Wang, Xin
    ULTRA CLEAN PROCESSING OF SEMICONDUCTOR SURFACES IX, 2009, 145-146 : 245 - 248
  • [42] CMOS Scaling for sub-90 nm to sub-10 nm
    Iwai, H
    17TH INTERNATIONAL CONFERENCE ON VLSI DESIGN, PROCEEDINGS: DESIGN METHODOLOGIES FOR THE GIGASCALE ERA, 2004, : 30 - 35
  • [43] A Nanogap Transducer Array on 32nm CMOS for Electrochemical DNA Sequencing
    Hall, Drew A.
    Daniels, Jonathan S.
    Geuskens, Bibiche
    Tayebi, Noureddine
    Credo, Grace M.
    Liu, David J.
    Li, Handong
    Wu, Kai
    Su, Xing
    Varma, Madoo
    Elibol, Oguz H.
    2016 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE (ISSCC), 2016, 59 : 288 - U400
  • [44] Revolutionary Nanoelectronic Devices and Processes for Post 32nm CMOS Era
    Nishi, Yoshio
    ADVANCED GATE STACK, SOURCE/DRAIN, AND CHANNEL ENGINEERING FOR SI-BASED CMOS 5: NEW MATERIALS, PROCESSES, AND EQUIPMENT, 2009, 19 (01): : 3 - 14
  • [45] Scaling Deep Trench Based eDRAM on SOI to 32nm and Beyond
    Wang, G.
    Anand, D.
    Butt, N.
    Cestero, A.
    Chudzik, M.
    Ervin, J.
    Fang, S.
    Freeman, G.
    Ho, H.
    Khan, B.
    Kim, B.
    Kong, W.
    Krishnan, R.
    Krishnan, S.
    Kwon, O.
    Liu, J.
    McStay, K.
    Nelson, E.
    Nummy, K.
    Parries, P.
    Sim, J.
    Takalkar, R.
    Tessier, A.
    Todi, R. M.
    Malik, R.
    Stiffler, S.
    Iyer, S. S.
    2009 IEEE INTERNATIONAL ELECTRON DEVICES MEETING, 2009, : 236 - 239
  • [46] Design for manufacturing strategies to bring silicon process to 32nm node
    Chen, JF
    Staud, W
    Arnold, B
    ISSM 2005: IEEE International Symposium on Semiconductor Manufacturing, Conference Proceedings, 2005, : 101 - 104
  • [47] Characterization of 32nm node BEOL grating structures using scatterometry
    Zangooie, Shahin
    Sendelbach, Matthew
    Angyal, Matthew
    Archie, Charles
    Vaid, Alok
    Matthew, Itty
    Herrera, Pedro
    METROLOGY, INSPECTION, AND PROCESS CONTROL FOR MICROLITHOGRAPHY XXII, PTS 1 AND 2, 2008, 6922 (1-2):
  • [48] 32nm node technology development using interference immersion lithography
    Sewell, H
    McCafferty, D
    Markoya, L
    Hendrickx, E
    Hermans, J
    Ronse, K
    Advances in Resist Technology and Processing XXII, Pt 1 and 2, 2005, 5753 : 491 - 501
  • [49] Double patterning design split implementation and validation for the 32nm node
    Drapeau, Martin
    Wiaux, Vincent
    Hendrickx, Eric
    Verhaegen, Staf
    Machida, Takahiro
    DESIGN FOR MANUFACTURABILITY THROUGH DESIGN-PROCESS INTEGRATION, 2007, 6521
  • [50] Multi-gate devices for the 32nm technology node and beyond
    Collaert, N.
    De Keersgieter, A.
    Dixit, A.
    Ferain, I.
    Lai, L. -S.
    Lenoble, D.
    Mercha, A.
    Nackaerts, A.
    Pawlak, B. J.
    Rooyackers, R.
    Schulz, T.
    San, K. T.
    Son, N. J.
    Van Dald, M. J. H.
    Verheyen, P.
    von Amim, K.
    Witters, L.
    De Meyer, K.
    Biesemans, S.
    Jurczak, M.
    ESSDERC 2007: PROCEEDINGS OF THE 37TH EUROPEAN SOLID-STATE DEVICE RESEARCH CONFERENCE, 2007, : 143 - +
12345