New constraint for Vth optimization for sub 32nm node CMOS gates scaling

被引：0
|
作者：
Morifuji, E [1 ]
Kapur, P [1 ]
Chao, AKA [1 ]
Nishi, Y [1 ]
机构：
[1] Stanford Univ, Dept Elect Engn, Ctr Integrated Syst, Stanford, CA 94305 USA
来源：
IEEE INTERNATIONAL ELECTRON DEVICES MEETING 2005, TECHNICAL DIGEST | 2005年
关键词：
D O I：
暂无
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
We show new constraint Of V-th scaling for logic blocks from inverter operation viewpoint. In lower V-th region, delay time in inverter chain saturates because of the loss in overdrive for the input of MOSFETs. This loss will dominate the inverter speed in scaled V-dd region and we propose a new relaxed scaling scenario. This accounts for the speed loss using a simplified model which adequately manifests the new phenomenon.
引用
收藏
页码：1049 / 1052
页数：4
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