Hardware/software co-design of a Java']Java co-processor for a 32-bit RISC system and the implementation of the hardware partition

被引：0
|
作者：
Fang, W [1 ]
Yu, Y [1 ]
Hou, XF [1 ]
Hao, M [1 ]
Dian, H [1 ]
机构：
[1] Fudan Univ, ASIC, Shanghai 200433, Peoples R China
来源：
2005 6TH INTERNATIONAL CONFERENCE ON ASIC PROCEEDINGS, BOOKS 1 AND 2 | 2005年
关键词：
D O I：
暂无
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
In this paper we proposed a design of a Java co-processor for a 32-bit RISC system to improve its performance, as the software only Java interpreter is more time-consuming. Our work includes the hardware/software co-design of the Java Card Virtual Machine (JCVM) and the details of its hardware implementation. The JCVM translates the Java bytecodes (JBCs) into the native RISC instructions and then passes them to the RISC core. A 16-byte pre-fetch FIFO and the folding mechanism are applied to further speedup the translation.
引用
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页码：243 / 246
页数：4
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