Effect of energy contamination on the p-channel transistor characteristics

被引:0
|
作者
Thanigaivelan, T
Ibrahim, K
Hai, LK
Shahril, N
Huzainy, M
Sani, A
机构
关键词
D O I
10.1109/SMELEC.2004.1620975
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
The Nwell and Pwell retrograde implants are high-energy implants requiring double charge implants for some cases. The energy contamination for double charge implant poses strict control on implanter performance, with critical control on the vacuum levels on the implanter. Even with well-controlled ultra high vacuum, the energy contamination is inevitable caused by pressure changes due to resist out gassing and vacuum integrity. This poses severe challenges in tool matching between High Energy (HE) and Medium Current (MC) implanters. For the same energy the single charge implant on a HE needs to be matched to the double charge implant on a MC implanter to provide manufacturing flexibility and better utilization in a foundry environment. To achieve that a novel three step approach has been reported in this paper, to match the bulk, surface and punch through characteristics of the PMOS short and long channel transistors.
引用
收藏
页码:677 / 681
页数:5
相关论文
共 50 条
  • [31] COMPARISON OF CHARACTERISTICS OF N-CHANNEL AND P-CHANNEL MOSFETS FOR VLSIS
    TAKEDA, E
    NAKAGOME, Y
    KUME, H
    SUZUKI, N
    ASAI, S
    IEEE TRANSACTIONS ON ELECTRON DEVICES, 1983, 30 (06) : 675 - 680
  • [32] EFFECT OF N-CHANNEL AND P-CHANNEL DOPING ON THE IV CHARACTERISTICS OF ALINAS-GAINAS HEMTS
    MISHRA, UK
    JELLOIAN, LM
    LUI, M
    THOMPSON, M
    ROSENBAUM, SE
    KIM, KW
    INSTITUTE OF PHYSICS CONFERENCE SERIES, 1992, (120): : 287 - 292
  • [33] Investigation of InP/In0.65Ga0.35As metamorphic p-channel doped-channel field-effect transistor
    Tsai, Jung-Hui
    SUPERLATTICES AND MICROSTRUCTURES, 2016, 95 : 83 - 87
  • [34] A p-channel MOS synapse transistor with self-convergent memory writes
    Diorio, C
    IEEE TRANSACTIONS ON ELECTRON DEVICES, 2000, 47 (02) : 464 - 472
  • [35] p-channel LDMOS transistor using new tapered field oxidation technology
    Kim, J
    Kim, SG
    Koo, JG
    Kim, DY
    ELECTRONICS LETTERS, 1998, 34 (19) : 1893 - 1894
  • [36] Simulation and analysis of heterostructures for normally-off p-channel GaN transistor
    Kozlovskaya, E. A.
    Kurbanbaeva, D. M.
    Tsarik, K. A.
    ST PETERSBURG POLYTECHNIC UNIVERSITY JOURNAL-PHYSICS AND MATHEMATICS, 2023, 16 (03): : 449 - 453
  • [37] Atomistic Modelling of p-channel Junctionless Silicon Nanowire Transistor: k.p approach
    Akhavan, N. D.
    Jolley, G.
    Umana-Membreno, G.
    Antoszewski, J.
    Faraone, L.
    2014 INTERNATIONAL CONFERENCE ON NANOSCIENCE AND NANOTECHNOLOGY (ICONN), 2014, : 17 - 20
  • [38] Characteristics of a Novel Poly-Si P-Channel Junctionless Thin-Film Transistor With Hybrid P/N-Substrate
    Cheng, Ya-Chi
    Chen, Hung-Bin
    Su, Jun-Ji
    Shao, Chi-Shen
    Thirunavukkarasu, Vasanthan
    Chang, Chun-Yen
    Wu, Yung-Chun
    IEEE ELECTRON DEVICE LETTERS, 2015, 36 (02) : 159 - 161
  • [39] Germanium-Tin P-Channel Tunneling Field-Effect Transistor: Device Design and Technology Demonstration
    Yang, Yue
    Han, Genquan
    Guo, Pengfei
    Wang, Wei
    Gong, Xiao
    Wang, Lanxiang
    Low, Kain Lu
    Yeo, Yee-Chia
    IEEE TRANSACTIONS ON ELECTRON DEVICES, 2013, 60 (12) : 4048 - 4056
  • [40] Self-aligned GaAs p-channel enhancement mode MOS heterostructure field-effect transistor
    Passlack, M
    Abrokwah, JK
    Droopad, R
    Yu, ZY
    Overgaard, C
    Yi, SI
    Hale, M
    Sexton, J
    Kummel, AC
    IEEE ELECTRON DEVICE LETTERS, 2002, 23 (09) : 508 - 510