Rail-to-rail complementary input StrongARM comparator for low-power applications

被引：4

作者：

Al-Qadasi, Mohammed A. ^{[1
]}

Alshehri, Abdullah ^{[1
]}

Alturki, Abdullah ^{[1
]}

Almansouri, Abdullah S. ^{[1
,2
]}

Salama, Khaled N. ^{[1
]}

Fariborzi, Hossein ^{[1
]}

Al-Attar, Talal ^{[1
]}

机构：

[1] King Abdullah Univ Sci & Technol, CEMSE, Thuwal, Saudi Arabia

[2] Univ Jeddah, Dept Elect & Elect Engn, Jeddah, Saudi Arabia

来源：

IET CIRCUITS DEVICES & SYSTEMS | 2020年 / 14卷 / 06期

关键词：

CMOS logic circuits; comparators (circuits); low-power electronics; microcontrollers; low-power applications; latch comparator; differential input PMOS transistors; rail-to-rail input range; low-energy consumption; rail-to-rail complementary input strong ARM latch comparator; cross-coupled NMOS transistors; energy harvested Internet of Thing applications; CMOS technology; post-layout simulations; chip measurements; energy; 15; 2; fJ; frequency; 3; 0; GHz; size; 65; nm;

D O I：

10.1049/iet-cds.2019.0361

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This study proposes a new scheme for rail-to-rail input StrongARM latch comparator. Additional differential input p-type metal-oxide-semiconductor (PMOS) and cross-coupled n-type metal-oxide-semiconductor (NMOS) transistors have been introduced to achieve the rail-to-rail input range. The proposed scheme offers low-energy consumption of 15.2 fJ and a high speed of 3 GHz, which makes it attractive for energy harvested Internet of Thing applications. The proposed architecture is fabricated in 65 nm complementary metal-oxide-semiconductor (CMOS) technology and the functionality is verified using post-layout simulations and chip measurements.

引用

页码：898 / 900

页数：3

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