A FPGA-based Architecture for Real-Time Image Matching

被引：2

作者：

Wang, Jianhui ^{[1
]}

Zhong, Sheng ^{[1
]}

Xu, Wenhui ^{[1
]}

Zhang, Weijun ^{[1
]}

Cao, Zhiguo ^{[1
]}

机构：

[1] Huazhong Univ Sci & Technol, Sch Automat, Sci & Technol Multispectral Informat Proc Lab, Wuhan 430074, Peoples R China

来源：

MIPPR 2013: PARALLEL PROCESSING OF IMAGES AND OPTIMIZATION AND MEDICAL IMAGING PROCESSING | 2013年 / 8920卷

关键词：

SIFT; BRIEF; Image matching; Field Programmable Gate Array (FPGA); SIFT;

D O I：

10.1117/12.2031050

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Image matching is a fundamental task in computer vision. It is used to establish correspondence between two images taken at different viewpoint or different time from the same scene. However, its large computational complexity has been a challenge to most embedded systems. This paper proposes a single FPGA-based image matching system, which consists of SIFT feature detection, BRIEF descriptor extraction and BRIEF matching. It optimizes the FPGA architecture for the SIFT feature detection to reduce the FPGA resources utilization. Moreover, we implement BRIEF description and matching on FPGA also. The proposed system can implement image matching at 30fps (frame per second) for 1280x720 images. Its processing speed can meet the demand of most real-life computer vision applications.

引用

页数：8

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