Electrical and Thermal Co-Design for High-Power FPGA Packages

This paper describes a systematic approach to design field-programmable gate array (FPGA) package for high-power applications. As the power consumption is up to multi-hundred watts, not only the heat dissipation becomes a challenge, but the temperature-induced reliability concerns also mount up in the high current and noise-sensitive packages. Two most profound phenomena are substrate electromigration (EM) and package decoupling capacitor time-dependent dielectric breakdown (TDDB). The impact of EM is on maximum current-carrying capability, and impact of TDDB is on voltage noise suppression capability. However, we find both traditional static way of EM calculation and the legacy design considerations are oversimplified and insufficient for high-power products. In this paper, we report an enhanced methodology to derive substrate EM failure rate from composite current and temperature distributions. Moreover, we incorporate capacitor TDDB into the design flow to optimize capacitor lifetime for effective voltage noise suppression. In the end, we apply the electrical and thermal code-sign to a 16-nm, 200-A, high-power FPGA meeting all current and dynamic noise specifications.