Three-Dimensional Dynamic Programming Accelerator for Multiple Sequence Alignment

被引：0

作者：

Chien, Ruei-Ting ^{[1
]}

Liao, Yi-Lun ^{[1
]}

Wang, Chien-An ^{[2
]}

Li, Yu-Cheng ^{[2
]}

Lu, Yi-Chang ^{[1
,2
]}

机构：

[1] Natl Taiwan Univ, Dept Elect Engn, Taipei, Taiwan

[2] Natl Taiwan Univ, Grad Inst Elect Engn, Taipei, Taiwan

来源：

2018 IEEE NORDIC CIRCUITS AND SYSTEMS CONFERENCE (NORCAS): NORCHIP AND INTERNATIONAL SYMPOSIUM OF SYSTEM-ON-CHIP (SOC) | 2018年

关键词：

Three sequence alignment; Three-dimensional programming; Needleman-Wunsch algorithm; Parallel processing elements; Hardware accelerator; MAFFT;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Three sequence alignment can be used to improve the accuracy of multiple sequence alignment in genomics. In this paper, we design a hardware accelerator for three-dimensional dynamic programming algorithm of three sequence alignment. By utilizing parallel processing elements, our design can find the optimal alignment scores in a shorter time than that required by software. In addition, we propose a memory-efficient slicing method for three-dimensional dynamic programming in order to process sequences of longer lengths. The hardware accelerator is implemented on both FPGA and ASIC. The ASIC implementation using TSMC 40nm technology can achieve at least 160x speedup over the software implementation.

引用

页数：5

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