Clock power issues in system-on-a-chip designs

The paper investigates some issues on clock power consumption in system-oil-a-chip (SoC) designs. Since clock power consumption is often the largest part of total chip power; research in this area becomes urgent. In a SoC, the clock power depends not only on clock distribution wiring, clock driver sizing and the capability to disable part of the clock network, bur also on circuit design style, architectural choice and the clock rate of the IP blocks. The different IP blocks may require that multiple frequency clocks are distributed on the chip. Our research provides a clock power model for SoC that takes into account these various factors. The impact of architectural, design, and logic style on clock power is studied using adder and register designs. In failure research, such characterizing information on SoC designs will be used in designing the clock network and estimating its power dissipation.