A High Resolution DPWM Based on Synchronous Phase-Shifted Circuit and Delay Line

被引：8

作者：

Cheng, Xin ^{[1
]}

Shao, Wanjing ^{[1
]}

Xu, Lixin ^{[2
]}

Zhang, Yongqiang ^{[1
]}

Xie, Guangjun ^{[1
]}

Zhang, Zhang ^{[1
]}

机构：

[1] Hefei Univ Technol, Sch Elect Sci & Appl Phys, Hefei 230601, Anhui, Peoples R China

[2] Cadence, Shanghai 200126, Peoples R China

来源：

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS | 2020年 / 67卷 / 08期

基金：

中国国家自然科学基金;

关键词：

Digital pulse width modulation; linearity; resolution; synchronous phase-shifted circuit; time resolution; DIGITAL PULSEWIDTH MODULATOR; WIDTH MODULATOR; CONVERTER; PWM;

D O I：

10.1109/TCSI.2020.2977146

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this paper, a hybrid architecture of digital pulse width modulator (DPWM) with high resolution is proposed. Furthermore, to enhance linearity performance, the critical path is optimized by a novel synchronous phase-shifted circuit. A carry chain-based delay line is also utilized to improve time resolution. A 14-bit DPWM with the proposed architecture is implemented and tested by Altera Cyclone IV FPGA. The experiment results show that the DPWM achieves high linearity, where R-2 maintains over 0.9994. Besides, the output duty cycle covers a wide range from 0.9429% to 99.2% and the time resolution is about 41.3ps.

引用

页码：2685 / 2692

页数：8

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