Interface Trap Density Estimation in FinFETs from the Subthreshold Current

被引：0
|
作者：
Schmitz, J. [1 ,4 ]
Kaleli, B. [1 ,2 ]
Kuipers, P. [1 ]
van den Berg, N. [1 ,3 ]
Smits, S. M. [1 ]
Hueting, R. J. E. [1 ]
机构：
[1] Univ Twente, MESA Inst nanotechnol, Enschede, Netherlands
[2] ASML, Veldhoven, Netherlands
[3] Micronit Microfluidies, Enschede, Netherlands
[4] Univ Twente, NL-7500 AE Enschede, Netherlands
来源：
2016 INTERNATIONAL CONFERENCE ON MICROELECTRONIC TEST STRUCTURES (ICMTS) | 2016年
关键词：
MOS devices; FinFETs; Current; Complementary MOSFETs (CMOSFETs); Traps; Interface states; FIELD-EFFECT TRANSISTORS; THIN-FILM; EXTRACTION; SLOPE; MODEL; NOISE;
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
In this work we present a measurement approach to determine the interface trap density in FinFETs as a function of their energy. It is based on the precise determination of the gate voltage dependent ideality factor of the subthreshold current in this device. The required measurement accuracy for temperature, drain current and transconductance is derived, and we propose an implementation for wafer-level device measurement on contemporary test set-ups. Exemplary interface trap distributions are shown as obtained from two FinFET device technologies, featuring the commonly observed bathtub shape.
引用
收藏
页码：164 / 167
页数：4
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