Series Resistance Effects on the Back-gate Biased Operation of Junctionless Transistors

被引：1
|
作者：
Jeon, Dae-Young [1 ]
Park, So Jeong [2 ]
Mouis, Mireille [3 ]
Barraud, Sylvain [4 ]
Kim, Gyu-Tae [2 ]
Ghibaudo, Gerard [3 ]
机构：
[1] Korea Inst Sci & Technol, Inst Adv Composite Mat, Joellabuk Do 55324, South Korea
[2] Korea Univ, Sch Elect Engn, Seoul 136701, South Korea
[3] Grenoble INP, IMEP LAHC, BP 257, F-38016 Grenoble, France
[4] CEA, LETI Minatec, 17 Rue Martyrs, F-38054 Grenoble, France
来源：
2019 JOINT INTERNATIONAL EUROSOI WORKSHOP AND INTERNATIONAL CONFERENCE ON ULTIMATE INTEGRATION ON SILICON (EUROSOI-ULIS) | 2019年
基金：
新加坡国家研究基金会;
关键词：
junctionless transistors; back biasing effects; series resistance; numerical simulation; NANOWIRE TRANSISTORS; SOI;
D O I：
10.1109/eurosoi-ulis45800.2019.9041921
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
Unique electrical properties of junctionless transistors (JLTs) with back-gate bias (V-gb) effects are investigated and visualized by numerical simulations. Charge coupling effects between front and back interfaces influenced threshold voltage (V-th) and flat-band voltage (V-fb) of JLTs. In addition, series resistance (R-sd) of JLTs was dependent on V-gb and back-biasing behavior of JLT with a shorter channel was deviated from intrinsic characteristics due to considerable R-sd effects. The R-sd was extracted by transfer length method (TLM) and its effects were de-embedded using simple equation.
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页数：4
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