Design of high-performance low-density parity-check codes using interleaver approach

被引：0
|
作者：
He, Z [1 ]
Fortier, P [1 ]
Roy, S [1 ]
机构：
[1] Univ Laval, Dept Elect & Comp Engn, Ste Foy, PQ G1K 7P4, Canada
来源：
ELECTRONICS LETTERS | 2005年 / 41卷 / 25期
关键词：
D O I：
10.1049/el:20053325
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
Interleaver description of parity-check matrix is proposed for the design of high-performance low-density parity-check (LDPC) codes. Based on the S-random interleaver and the dividable S-random interleaver used in turbo codes, two classes of LDPC codes, the g-random codes and the g-random structured codes, are proposed to improve the performance in the waterfall region and slow down the onset of the error floor.
引用
收藏
页码：1390 / 1391
页数：2
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