On the computational synthesis of CMOS voltage followers

被引：12

作者：

Tlelo-Cuautle, E ^{[1
]}

Torres-Muñoz, D

Torres-Papaqui, L

机构：

[1] INAOE MEXICO, Dept Elect, Integrated Circuit Desing Grp, Puebla 72000, Mexico

[2] INAOE, CONACyT, Puebla 72000, Mexico

来源：

IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES | 2005年 / E88A卷 / 12期

关键词：

CAD; analog synthesis; voltage follower; nullator; norator; biasing and sizing; MOSFET;

D O I：

10.1093/ietfec/e88-a.12.3479

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

A systematic method is introduced to the computational synthesis of CMOS voltage followers (VFs). The method is divided in three steps: generation of the small-signal circuitry by selection of nullators to model the behavior of a VF, and addition of norators to form nullator-norator joined-pairs; generation of the bias circuitry by addition of ideal biases according to the properties of nullators and norators; and synthesis of the joined-pairs by MOSFETs, and of the current-biases by CMOS current mirrors. It is shown that the proposed synthesis method has the capability to generate already known and new CMOS VF topologies.

引用

页码：3479 / 3484

页数：6

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