A novel hardware implementation of MP3 decoder for low power and minimum chip size

被引：0

作者：

Yang, JT ^{[1
]}

Yu, JM ^{[1
]}

机构：

[1] TaHwa Inst Technol, Hsinchu, Taiwan

来源：

2005 6th International Conference on ASIC Proceedings, Books 1 and 2 | 2005年

关键词：

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

The new structure presented in this paper is for the hardware implementation of MP3 decoder. The purpose is to achieve a controller IC with low power consumption, small chip size and flexible choice of peripheral flash memory. DSP is not required in this design, but a simple 8-bit micro controller is used instead. The specific hardware circuits can lower the system frequency to save power, and some techniques are applied to reduce the embedded memory.

引用

页码：1062 / 1065

页数：4

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