High efficiency LDMOS power FET for low voltage wireless communications

被引：14
|
作者：
Ma, G
Burger, W
Dragon, C
Gillenwater, T
机构：
来源：
IEDM - INTERNATIONAL ELECTRON DEVICES MEETING, TECHNICAL DIGEST 1996 | 1996年
关键词：
D O I：
10.1109/IEDM.1996.553129
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
High efficiency, high gain power transistors are required to meet RF performance and output power specifications as new generation portable communication products move towards lower voltage operations. A low cost, high efficiency silicon MOSFET using RFLDMOS (LV2) technology was developed In Motorola to operate at 3.4-12.5V drain voltages. The LV2 device can deliver 70% power added efficiency with 12 dB gain, 31.5 dBm output power at 3.4V and 850 MHz. This is the best known RF performance far silicon devices at 3.4V. This paper will focus on 3.4V LV2 device optimization and performance.
引用
收藏
页码：91 / 94
页数：4
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