TID Response of Nanowire Field-Effect Transistors: Impact of the Back-Gate Bias

The impact of back-gate bias on the total ionizing dose (TID) response of silicon-on-insulator (SOI) nanowire field-effect transistors (NWFETs) is investigated. The voltage shift induced by TID is studied using different NWFET geometries and as function of the bias applied to the back-gate made of the silicon substrate. Modifications induced on static electrical characteristics, that is, drain current versus gate-to-source voltage I-D(V-GS) characteristics, are investigated. Experimental results highlight that the bias applied to the back-gate during I- V measurements strongly impacts the NWFET TID response. At 0 V applied to the back-gate, a usual TID behavior is observed. I- V curves are shifted to negative V-GS values, which is consistent with the literature. In contrast, two competing mechanisms are shown when negative biases are applied to the back-gate. I-D(V-GS) curves are first shifted to positive V-GS values for low TID before showing a more usual negative TID-induced voltage shifts. This two-step behavior may be attributed to several phenomena. They include either a modification of the net trapped charge sign for several back-gate biases and/or a motion of carriers trapped into the Buried OXide (BOX). The major goal of this article is to identify the mechanism at stake which drives this combined TID/electrostatic behavior.