Binary decision diagrams for efficient hardware implementation of fast IP routing lookups

With an immense continuous growth in the Internet traffic, the demand for routers that perform IP routing at high speed and throughput is ever increasing. The key issue in the router performance is the IP routing lookup mechanism based on the longest prefix matching scheme. Earlier works on fast IPv4 routing table lookup are based on Content Addressable Memory (CAM), memory lookups and the CPU caching. These schemes depend on the memory access technology which limits their performance. Besides, these address lookup schemes designed for the IPv4 32-bit address mostly are not extensible to adapt to the forthcoming IPv6 where the IP address is 128 bits long. The paper presents a Binary Decision Diagrams based optimized combinational logic for an efficient implementation of fast address lookup scheme in reconfigurable hardware. The experimental results show that, for the 32-bit IP address large MAE-east routing table, the number of redundant nodes is more than 99.99% in constructing the binary decision tree. With the binary encoding of the output part, an additional 36% reduction is obtained in the number of effective nodes. Besides the performance of the scheme, routing table update and the scalability to IPv6 issues are discussed.