IMPROVEMENT OF POWER EFFICIENCY AND OUTPUT VOLTAGE RIPPLE OF EMBEDDED DC-DC CONVERTERS WITH THREE STEP DOWN RATIOS

被引：3

作者：

Bhattacharyya, Kaushik ^{[1
]}

Kumar, P. V. Ratna ^{[1
]}

Mandal, Pradip ^{[1
]}

机构：

[1] IIT Kharagpur, Dept E&ECE, Kharagpur 721302, W Bengal, India

来源：

JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS | 2012年 / 21卷 / 01期

关键词：

Current regulation; embedded DC-DC converter; improvement of power efficiency; low output voltage ripple; nonoverlapped rotational time interleaving (NRTI) switching scheme; shoot through current elimination; three step down outputs; CAPACITOR; CHIP;

D O I：

10.1142/S0218126612500077

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

In this paper three embedded switched capacitor based DC-DC converters targeting Vdd/2, 2Vdd/3, and Vdd/3 output voltages have been designed with improved power efficiency and output voltage ripple. The performance of each of the converter is improved by nonoverlapped rotational time interleaving (NRTI) switching scheme. Current regulation scheme is included with each of the above NRTI switched capacitor converter to achieve better load and line regulation. The proposed converters are designed and simulated in a 0.18 mu m n-well CMOS process with the total flying capacitance of 330 pF and load capacitor of 50 pF. The capacitance values are kept within on-chip implementable range. The maximum power efficiency and the output voltage ripple of the integrated NRTI DC-DC converters targeted for Vdd/2, 2Vdd/3 and Vdd/3 output generation are 71.5% and 5 mV, 69.23% and 13.27 mV and 58.09% and 10.5 mV, respectively.

引用

页数：22

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