Implementation and Verification of MASH 1-1-1 for Fractional-N Frequency synthesizer in Zynq-7000 series SoC Platform

被引：0

作者：

Perumal, Mailerum S. ^{[1
]}

Karthigeyan, K. A. ^{[1
]}

Chandramani, Premanand V. ^{[1
]}

机构：

[1] SSN Coll Engn, Dept Elect & Commun Engn, Chennai 603110, Tamil Nadu, India

来源：

PROCEEDINGS OF 2ND INTERNATIONAL CONFERENCE ON 2017 DEVICES FOR INTEGRATED CIRCUIT (DEVIC) | 2017年

关键词：

Phase Noise; spur; fractional division ratio; MASH; Delta Sigma Modulator; SoC; FPGA; Zynq; 7000; Series; DELTA-SIGMA MODULATOR; BAND; VCO;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

The Delta-Sigma Modulator (DSM) is predominantly used to control the fractional division part of the PLL based Fractional-N Frequency Synthesizer. In this paper a third order Multi Stage Noise Shaping (MASH) Delta-Sigma Modulator architecture is designed using Verilog code. Simulated output is implemented in a SoC based Field programmable gate array (FPGA), Zynq 7000 series and output is verified using DSO.

引用

页码：825 / 829

页数：5

共 21 条

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