25-nm p-channel vertical MOSFET's with SiGeC source-drains

被引：32

作者：

Yang, M ^{[1
]}

Chang, CL ^{[1
]}

Carroll, M ^{[1
]}

Sturm, JC ^{[1
]}

机构：

[1] Princeton Univ, Dept Elect Engn, Princeton, NJ 08544 USA

来源：

IEEE ELECTRON DEVICE LETTERS | 1999年 / 20卷 / 06期

关键词：

D O I：

10.1109/55.767105

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

The scaling of vertical p-channel MOSFET's with the source and drain doped with boron during low temperature epitaxy is limited by the diffusion of boron during subsequent side wall gate oxidation. By introducing thin SiGeC layers in the source and drain regions, this diffusion has been suppressed, enabling for the first time the scaling of vertical p-channel MOSFET's to under 100 nm in channel length to be realized. Device operation with a channel length down to 25 nm has been achieved.

引用

页码：301 / 303

页数：3

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