A high-speed latched comparator with low offset voltage and low dissipation

被引：13

作者：

Zhu, Zhangming ^{[1
]}

Yu, Guangwen ^{[1
]}

Wu, Hongbing ^{[1
]}

Zhang, Yifei ^{[1
]}

Yang, Yintang ^{[1
]}

机构：

[1] Xidian Univ, Sch Microelect, Xian 710071, Peoples R China

来源：

ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING | 2013年 / 74卷 / 02期

基金：

中国国家自然科学基金;

关键词：

Latched comparator; Positive feedback; Transmission gate; Monte Carlo analysis; High-speed; Low offset voltage; Low dissipation;

D O I：

10.1007/s10470-012-9999-0

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

An ultra high-speed latched comparator using a controlled amount of positive feedback cell has been designed in TSMC 0.18 mu m CMOS technique. Transmission gate (TG) switches are used to implement the preamplifier circuit. The use of TG switches results in a reduction in the power consumption of the high-speed comparator as well as clock feedthrough and the effect of charge injection. The simulation results demonstrate that it can work at 1.25 GHz suitable for high speed applications, and consumes 273.6 mu W with a power supply of 1.8 V at 100 MHz and Monte Carlo simulation shows that the comparator has a low offset voltage approximately 0.499 mV.

引用

页码：467 / 471

页数：5

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