Energy Efficient Reconfigurable Fir Filter Architecture

被引：0
|
作者：
Quraishi, Mahvish [1 ]
Alagdeve, V. D. [1 ]
机构：
[1] YC Coll Engn, Elect Engn Dept, Nagpur, Maharashtra, India
来源：
2017 INTERNATIONAL CONFERENCE ON COMMUNICATION AND SIGNAL PROCESSING (ICCSP) | 2017年
关键词：
Finite impulse response (FIR); reconfigurable architecture; multiple constant multiplications (MCM); LOW-COMPLEXITY; SYSTOLIZATION; FPGA;
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
In finite impulse response (FIR) filters reconfigurability and low complexity are the two key requirements. In this paper FIR filter in transpose form with inherent pipelining are used to save computation time. A flow graph for transpose form block FIR filter with reduced complexity is derived on detail analysis of computation of transpose form block FIR filter. A generalised architecture which is multiplier based is derived for proposed transpose form block FIR filter for reconfigurable applications. A less complex design using multiple constant multiplications (MCM) method for block implementation of fixed FIR filter is also introduced.
引用
收藏
页码：509 / 513
页数：5
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