PDP and TPD Flexible MCML and MTCML Ultralow-Power and High-Speed Structures for Wireless and Wireline Applications

This article presents two novel structures for designing current mode logic (CML) digital circuits [MOS CML (MCML) and multiple tail CML (MTCML)] in ultralow-power (ULP) and high-speed (HS) applications. The transistor's bulk can be used as a digital signal input at a level, where it does not cause a disturbance to the operation of the transistor. Therefore, the number of transistors used in novel structures is reduced and it is possible to improve power delay product (PDP) and time propagation delay (TPD) in some of the tail currents. This technique is obtained through integrating the bulk-driven technique into the CML digital circuits, which are in the form of bulk-driven MCML (BD-MCML) and BD-MTCML. In the conventional CMOS technology, the proposed structures depend on the type of substrate. The BD-MCML structure uses a deep n-well technology and the BD-MTCML uses an n-well technology. The CML gates, such as AND, XOR, and D-latch, are suggested. The systematic use of the proposed structures is discussed in both HS and ULP applications. Finally, an unsigned multiplier is designed in the form of the BD-MTCML with a conventional 180-nm technology. Mixed-signal circuits are Serial/De-serial (SerDes), optical receivers, radio frequency (RF) receivers, and line drivers on the HS approach, and also video processors and A/D and D/A converters on the ULP approach.