Cycle-based timing simulations using event-streams

A new logic-timing simulation algorithm, applicable to cycle-based simulation of acyclic combinational logic blocks or synchronous logic designs, is described and implemented. The algorithm is based opt evaluating ordered sequences of events, called Event-streams, instead of individual events as in a traditional event-driven simulator This allows very efficient gate evaluations using states unrolling and look-ahead processing. When processing long event-streams, the performance of our simulator can approach that of a compiled-code simulator without the poor instruction-cache behavior of large compiled-code simulations. In addition, the simulator can perform multi-cycle simulations that result in longer event-streams, which enhances the efficiency of gate evaluations. Experimental results show that our simulator runs about four rimes faster than the Verilog-XL simulator.