共 50 条
- [1] A fast SVM scheme for five-level diode-clamped inverters with balanced capacitor voltages and reduced switching frequency Diangong Jishu Xuebao/Transactions of China Electrotechnical Society, 2013, 28 (05): : 233 - 242
- [2] Balancing Control of DC-Link Capacitor Voltages for Five-Level Hybrid Diode-Clamped Inverters With Passive Front-Ends IEEE ACCESS, 2025, 13 : 45577 - 45593
- [3] Voltage balance boundary of five-level diode clamped inverters Diangong Jishu Xuebao/Transactions of China Electrotechnical Society, 2008, 23 (01): : 77 - 83
- [4] A novel diode clamped five-level inverter topology with the inner loop DC-bus clamped Diangong Jishu Xuebao/Transactions of China Electrotechnical Society, 2010, 25 (11): : 100 - 106
- [6] A Simple Double Mapping Based SVPWM Method for Balancing DC-Link Capacitor Voltages of Five-Level Diode-Clamped Converters APEC 2016 31ST ANNUAL IEEE APPLIED POWER ELECTRONICS CONFERENCE AND EXPOSITION, 2016, : 2806 - 2812
- [8] A Closed-Loop Voltage Balance Method for Five-Level Diode-Clamped Inverters IECON 2017 - 43RD ANNUAL CONFERENCE OF THE IEEE INDUSTRIAL ELECTRONICS SOCIETY, 2017, : 503 - 508
- [9] Stabilization of DC link voltage using redundant vectors for five-level diode clamped shunt active power filter 2013, World Scientific and Engineering Academy and Society, Ag. Ioannou Theologou 17-23, Zographou, Athens, 15773, Greece (12):