An Embedded Dynamically Self-Reconfigurable Master-Slaves MPSoC Architecture

A dynamically sefl-reconfigurable Master-Slaves MPSoC architecture framework is introduced which can be fully embedded into a single FPGA device. The Master core can request a Configuration Manager module to add, or remove, a slave core at runtime. If the request can be satisfied, self-reconfiguration commences, implemented by a pipeline of light-weight specialized blocks. The M-S architecture utilizes a simple and general token-based bus control mechanism that is reconfiguration aware. All system modules have been described in synthesizable VHDL. A first system prototype has been built and validated using the affordable XUP XC2VP30 board. Even when using CRC check of bitstreams dynamic reconfiguration can proceed at the maximum speed that can be supported by the ICAP Xilinx interface. The reconfiguration support logic consumes as little as 1012 slices on the Virtex II Pro FPGA.