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- [11] Reusing learned information in SAT-based ATPG 20TH INTERNATIONAL CONFERENCE ON VLSI DESIGN, PROCEEDINGS: TECHNOLOGY CHALLENGES IN THE NANOELECTRONICS ERA, 2007, : 69 - +
- [12] SAT-Based Test Pattern Generation with Improved Dynamic Compaction 2014 27TH INTERNATIONAL CONFERENCE ON VLSI DESIGN AND 2014 13TH INTERNATIONAL CONFERENCE ON EMBEDDED SYSTEMS (VLSID 2014), 2014, : 56 - 61
- [14] Improving test pattern compactness in SAT-based ATPG PROCEEDINGS OF THE 16TH ASIAN TEST SYMPOSIUM, 2007, : 445 - 450
- [15] Efficient SAT-based Dynamic Compaction and Relaxation for Longest Sensitizable Paths DESIGN, AUTOMATION & TEST IN EUROPE, 2013, : 448 - 453
- [16] A Novel SAT-based ATPG Approach for Transition Delay Faults 2017 IEEE INTERNATIONAL HIGH LEVEL DESIGN VALIDATION AND TEST WORKSHOP (HLDVT), 2017, : 17 - 22
- [17] Evaluating the Effectiveness of D-chains in SAT-based ATPG 2017 18TH IEEE LATIN AMERICAN TEST SYMPOSIUM (LATS 2017), 2017,
- [18] A Highly Fault-Efficient SAT-Based ATPG Flow IEEE DESIGN & TEST OF COMPUTERS, 2012, 29 (04): : 63 - 70
- [19] SAT-based ATPG for Path Delay Faults in sequential circuits 2007 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-11, 2007, : 3671 - 3674
- [20] Efficiency of Multi-Valued Encoding in SAT-based ATPG ISMVL 2006: 36th International Symposium on Multiple-Valued Logic, 2006, : 147 - 152