A New State Model for DRAMs Using Petri Nets

被引：0

作者：

Jung, Matthias ^{[1
]}

Kraft, Kira ^{[2
]}

Wehn, Norbert ^{[2
]}

机构：

[1] Fraunhofer IESE, D-67663 Kaiserslautern, Germany

[2] Univ Kaiserslautern, D-67663 Kaiserslautern, Germany

来源：

INTERNATIONAL CONFERENCE ON EMBEDDED COMPUTER SYSTEMS: ARCHITECTURES, MODELING, AND SIMULATION (SAMOS 2017) | 2017年

基金：

欧盟地平线“2020”;

关键词：

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

The functionality of DRAMs, especially the state transitions are described in JEDEC standards. These standards contain a finite state machine, which intends to provide an overview of the possible state transitions and the commands to control them. However, today's DRAMs are highly concurrent devices as they provide bank parallelism. The state diagram used in JEDEC standards does not model this concurrency and furthermore it is misleading in several aspects. In this paper, for the first time we present an easily comprehensive model of the DRAM states and transitions, using a Petri Net, which covers also the DRAM concurrency.

引用

页码：221 / 226

页数：6

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