Translating Traditional SIMD Instructions to Vector Length Agnostic Architectures

被引：0

作者：

Fu, Sheng-Yu ^{[1
]}

Hsu, Wei-Chung ^{[1
]}

机构：

[1] Natl Taiwan Univ, Taipei, Taiwan

来源：

PROCEEDINGS OF THE 2019 IEEE/ACM INTERNATIONAL SYMPOSIUM ON CODE GENERATION AND OPTIMIZATION (CGO '19) | 2019年

关键词：

Dynamic Binary Translation; SIMD; VLA;

D O I：

暂无

中图分类号：

TP31 [计算机软件];

学科分类号：

081202 ; 0835 ;

摘要：

One interesting trend of SIMD architecture is towards Vector Length Agnostic (VLA) designs. For example, ARM new vector ISA, Scalable Vector Extension (SVE), and RISC-V vector extension are adopting such a direction. VLA decouples the vector register length from the compiled binary so that the same executable could run on different implementations of vector length. However, in the current application world, the majority of SIMD code is fixed-length based, such as ARM-NEON, x86-SSE, x86-AVX, and traditional vector machines. Therefore, how to migrate legacy SIMD code to VLA architecture would be an interesting and important technical challenge.

引用

页码：275 / 275

页数：1

共 27 条

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