Design and implementation of reversible integer quaternionic paraunitary filter banks on adder-based distributed arithmetic

被引：0
|
作者：
Petrovsky, Nick A. [1 ]
Rybenkov, Eugene V. [1 ]
Petrovsky, Alexander A. [1 ]
机构：
[1] Belarusian State Univ Informat & Radioelect, Dept Comp Engn, Minsk, BELARUS
来源：
2017 SIGNAL PROCESSING: ALGORITHMS, ARCHITECTURES, ARRANGEMENTS, AND APPLICATIONS (SPA 2017) | 2017年
关键词：
adder-based distributed arithmetics; FPGA; integer quaternionic paraunitary filter banks;
D O I：
暂无
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
This paper presents a design method of reversible integer quaternionic paraunitary filter banks (Int-Q-PUFB) using the adder-based distributed arithmetic (DA(Sigma)) for implementation multiplier block-lifting structure modules. The proposed quaternion multiplier (Q-MUL) and 8-channel Int-Q-PUFB processors are implemented on the FPGA Xilinx Zynq 7010. The total magnitude response of analysis-synthesis system based on the given Int-Q-PUFB shows that the 8-channel 8 x 24 Int-Q-PUFB is perfect reconstruction filter bank for finite precision. Compared to known solutions of Int-Q-PUFB using block-lifting structure based on the CORDIC devices and ROM-based distributed arithmetic the given DA(Sigma)-based Int-Q-PUFB have more less implementation complexity and latency.
引用
收藏
页码：17 / 22
页数：6
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