A direct digital frequency synthesizer with single-stage delta-sigma interpolator and current-steering DAC

被引：0
|
作者：
Ni, WN [1 ]
Dai, FF [1 ]
Shi, Y [1 ]
Jaeger, RC [1 ]
机构：
[1] Chinese Acad Sci, Inst Semicond, Beijing 100083, Peoples R China
来源：
2005 Symposium on VLSI Circuits, Digest of Technical Papers | 2005年
关键词：
DDFS; delta-sigma interpolator; CMOS; DAC; Q(2) Random Walk;
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
This paper presents a direct digital frequency synthesizer (DDFS) with a 16-bit accumulator, a 4th-order single-stage pipelined delta-sigma interpolator and a 300MS/s 12-bit current-steering DAC based on Q(2) Random Walk switching scheme. The delta-sigma interpolator is used to reduce the phase truncation error and the ROM size. The measured spurious-free dynamic range (SFDR) is greater than 80 dB for 8-bit phase value and 12-bit sine-amplitude output. The DDFS prototype is fabricated in a 0.35um CMOS technology with core area of 1.11mm(2).
引用
收藏
页码：56 / 59
页数：4
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