Development of Exposed Die Large Body to Die Size Ratio Wafer Level Package Technology

被引:0
|
作者
Osenbach, J. [1 ]
Emerich, S. [1 ]
Golick, L. [1 ]
Cate, S. [2 ]
Chan, M. [3 ]
Yoon, S. W. [3 ]
Lin, Y. J. [4 ]
Wong, K. [5 ]
机构
[1] LSI Corp USA, Allentown, PA 18109 USA
[2] LSI Corp USA, San Jose, CA 95131 USA
[3] STATSChipPAC Ltd, Singapore 768442, Singapore
[4] STATSChipPAC Ltd, Singapore 738068, Singapore
[5] STATSChipPAC Inc, Fremont, CA 94538 USA
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暂无
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Traditionally fan out wafer level package technology has been associated with lower power, smaller body sizes (typically < 8mmx8mm), small body-to-die size area ratios (< 2) and fine pitch BGAs (0.4mm or less). This work extends this technology to larger body sizes up to 13mm x 13mm, higher powers, > 5W, and larger body-to-die size area ratios up to 10.5. It is shown that such packages can be readily manufactured in a 300mm wafer format with yields exceeding 99% and final package warpage < 75um. Further, data is presented showing that 10mm x 10mm packages with a body to die area ratio of 6.25 are compatible with moisture sensitivity level 1, and easily pass 2000 temperature cycle (-55C to 125C air to air) and 288 hr uHAST. That is to say they have reliability that is compatible with that required for all storage and communications applications. Larger package sizes, up to 13mm x 13mm, and body-to-die area ratios, > 10, have also been demonstrated. However, failures in extended temperature cycle were found in these larger packages. All of the failures were due to pre-identified package design flaws that violated well established rules. This indicates if such packages were designed with no rule violations then they would meet the reliability requirements needed for communications and storage applications.
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页码:952 / 955
页数:4
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