Turbo decoding of product codes for Gigabit per second applications and beyond

The main purpose of this paper is to present a new turbo decoding architecture for high data rates with strong error correction power. We present the latest results on the block turbo decoder designs of product codes, using extended BCH codes correcting one and three errors. We present the architecture for decoding the product code BCH (32,26,4) circle times BCH (32,26,4) as well as the architecture for decoding the product code BCH (128,106,8) circle times BCH (128,106,8). In both cases, we use the concept of a parallel decoding architecture which stores several data at the same memory address (RAM). The decoder designs are based on soft input-soft output (SISO) decoding, processing m = 2, 4 and 8 data simultaneously in order to increase the data rate. By using m elementary decoders processing m data at the same time, this new architecture increases the data rate by a factor m(2), the area of the m elementary decoders being approximately increased by a factor m(2)/2. But this new architecture uses only one RAM for decoding while a traditional design uses m memories. In this paper, we compare the most important characteristics of the new design with those of a traditional architecture. To compare the performance and complexity of the decoders, we use C language for behavioural simulations, VHDL for functional simulations and Synopsys Design Compiler for the synthesis. Copyright (c) 2005 AEIT.