A high speed self-biased CMOS amplifier IP core

被引：5
|
作者：
Zhu, ZM [1 ]
Liu, LX [1 ]
Yang, YT [1 ]
机构：
[1] Xidian Univ, Microelect Inst, Xian 710071, Peoples R China
来源：
PROCEEDINGS OF 2005 IEEE INTERNATIONAL WORKSHOP ON VLSI DESIGN AND VIDEO TECHNOLOGY | 2005年
关键词：
D O I：
10.1109/IWVDVT.2005.1504450
中图分类号：
TP301 [理论、方法];
学科分类号：
081202 ;
摘要：
A novel high speed 0.25um CMOS amplifier IP core is presented which use the complementary self-biasing differential amplifier technique. The proposed amplifier features a 418MHz unity gain frequency and 375V/us slew rate with capacitive load 2pF. The output voltage of the proposed amplifier swings from Vgnd to Vdd and the static power less than 0.32muW. A Verilog-A behavioral model is presented for the amplifier IP core which contains the important non-idealities of the amplifier.
引用
收藏
页码：6 / 9
页数：4
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