A Programmable Logic Controller Timer System Based on Parallel Operation

According to the work principle of small PLC, the timer operation instruction, this paper puts forward a parallel algorithm using the FPGA design a small PLC timing system. describes the design principle of the timer system, and the simulation of the system design vivificates timer and its function. The design and manufacture process of users in program execution module programmable logic controller (PLC) in RAM memory unit operation, not the timer, it with only a few execution time programmable logic controller (PLC) of user programs.