共 50 条
- [31] Processor array design for deep packet classification [J]. PROCEEDINGS OF THE FOURTH IEEE INTERNATIONAL SYMPOSIUM ON SIGNAL PROCESSING AND INFORMATION TECHNOLOGY, 2004, : 81 - 84
- [32] Fast IP packet classification with configurable processor [J]. GLOBECOM '01: IEEE GLOBAL TELECOMMUNICATIONS CONFERENCE, VOLS 1-6, 2001, : 2268 - 2274
- [34] Power optimized packet buffering in a protocol processor [J]. ICECS 2003: PROCEEDINGS OF THE 2003 10TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS, VOLS 1-3, 2003, : 1026 - 1029
- [36] An architecture for wireless LAN/MAN packet processor [J]. VTC2004-FALL: 2004 IEEE 60TH VEHICULAR TECHNOLOGY CONFERENCE, VOLS 1-7: WIRELESS TECHNOLOGIES FOR GLOBAL SECURITY, 2004, : 3206 - 3209
- [37] A study for packet buffer algorithms for a protocol processor [J]. THIRD INTERNATIONAL CONFERENCE ON INFORMATION TECHNOLOGY AND APPLICATIONS, VOL 1, PROCEEDINGS, 2005, : 587 - 590
- [38] Packet-by-packet all-optical burst-mode 3R regeneration in an optical-label switching router [J]. 2006 OPTICAL FIBER COMMUNICATION CONFERENCE/NATIONAL FIBER OPTIC ENGINEERS CONFERENCE, VOLS 1-6, 2006, : 2516 - 2518
- [39] A packet handoff management using partial buffer sharing scheme in wireless packet communications [J]. WORLD MULTICONFERENCE ON SYSTEMICS, CYBERNETICS AND INFORMATICS, VOL 1, PROCEEDINGS: INFORMATION SYSTEMS DEVELOPMENT, 2001, : 124 - 129