A 69-dB SNDR 300-MS/s Two-Time Interleaved Pipelined SAR ADC in 16-nm CMOS FinFET With Capacitive Reference Stabilization

被引：33

作者：

Martens, Ewout ^{[1
]}

Hershberg, Benjamin ^{[1
]}

Craninckx, Jan ^{[1
]}

机构：

[1] Interuniv Microelect Ctr, B-3001 Leuven, Belgium

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 2018年 / 53卷 / 04期

关键词：

ADC; FinFET technology; pipelined SAR ADC; reference pre-charging; reference ripple; reference stabilization; DB SNDR; 10-BIT;

D O I：

10.1109/JSSC.2017.2784762

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A two-time interleaved pipelined SAR ADC in 16-nm CMOS achieving 11.2-bit ENOB at 300 MS/s is presented. To cancel the signal-dependent voltage ripple on the reference node due to DAC switching, it employs a stabilization scheme based on the use of auxiliary DACs. The charge drawn from the reference becomes signal-independent, greatly reducing the requirements for the reference decoupling capacitance and/or buffers. The technique improves the linearity to levels better than 76-dB harmonic distortion. Power consumption is only 3.6 mW resulting in peak FoMs of 175.5 dB and 5.1 fJ/conv.step.

引用

页码：1161 / 1171

页数：11