Methods for Improving Power and Bandwidth of Power Hardware-in-the-Loop Testbenches

被引:0
|
作者
Garcia-Martinez, Eduardo [1 ]
Sanz-Osorio, Jose F. [2 ]
Munoz-Cruzado-Alba, Jesus [1 ]
Manuel Perie, Juan [1 ]
机构
[1] CIRCE Technol Ctr, Elect Syst Dept SSEE, Zaragoza, Spain
[2] Univ Zaragoza, Inst Univ Invest CIRCE, Zaragoza, Spain
基金
欧盟地平线“2020”;
关键词
Power Hardware-in-the-Loop (PHIL); Digital Real-Time Simulation (DRTS); Power Amplifier (PA); simulation; electrical power systems; SIMULATION;
D O I
10.1109/CPE-POWERENG54966.2022.9880861
中图分类号
TE [石油、天然气工业]; TK [能源与动力工程];
学科分类号
0807 ; 0820 ;
摘要
The integration of renewable energy into the electric grid is increasing the use of complex power grid systems. These systems need to be tested in order to guarantee a reliable and secure operation of the grid. A promising test technique to verify and validate these systems is Power Hardware-in-the-loop (PHIL), which can reproduce the desired working environment as closely as possible to real world conditions. However, the reduced bandwidth of the PHIL testbenches limit the accuracy of the experiments and can cause instability issues that compromise the test. In this paper, a characterization and analysis of the complete closed-loop block diagram of a PHIL test is made. After that, different methods are set forth and described to increase the bandwidth and power of the current PHIL testbenches.
引用
收藏
页数:6
相关论文
共 50 条
  • [1] Improving existing methods for stable and more accurate Power Hardware-in-the-Loop experiments
    Markou, A.
    Kleftakis, V.
    Kotsampopoulos, P.
    Hatziargyriou, N.
    [J]. 2017 IEEE 26TH INTERNATIONAL SYMPOSIUM ON INDUSTRIAL ELECTRONICS (ISIE), 2017, : 496 - 502
  • [2] Interface Compensation for Power Hardware-in-the-Loop
    Marks, Nathan D.
    Kong, Wang Y.
    Birt, Daniel S.
    [J]. 2018 IEEE 27TH INTERNATIONAL SYMPOSIUM ON INDUSTRIAL ELECTRONICS (ISIE), 2018, : 413 - 420
  • [3] Power System Network Reduction for Power Hardware-in-the-Loop Simulation
    Wang, Bin
    Hoke, Andy
    Tan, Jin
    [J]. 2021 IEEE KANSAS POWER AND ENERGY CONFERENCE (KPEC), 2021,
  • [4] Prototyping and Testing Power Electronics Systems using Controller Hardware-In-the-Loop (HIL) and Power Hardware-In-the-Loop (PHIL) Simulations
    Lemaire, Michel
    Sicard, Pierre
    Belanger, Jean
    [J]. 2015 IEEE VEHICLE POWER AND PROPULSION CONFERENCE (VPPC), 2015,
  • [5] Hardware-in-the-loop testing of digital power controllers
    Jiang, ZH
    Dougal, RA
    Leonard, R
    Figueroa, H
    Monti, A
    [J]. APEC 2006: TWENTY-FIRST ANNUAL IEEE APPLIED POWER ELECTRONICS CONFERENCE AND EXPOSITION, VOLS 1-3, 2006, : 901 - 906
  • [6] POWER HARDWARE-IN-THE-LOOP (PHIL) BASED ON FPGA
    Gehrke, Camila S.
    Oliveira, Alexandre C.
    Lima, Antonio Marcus N.
    da Silva, Italo Roger F. M. P.
    [J]. 2013 BRAZILIAN POWER ELECTRONICS CONFERENCE (COBEP), 2013, : 298 - 304
  • [7] A Power Hardware-in-the-loop Emulation of a Faulted Inverter
    Boby, Mathews
    Pillay, Pragasen
    [J]. 2019 IEEE INTERNATIONAL ELECTRIC MACHINES & DRIVES CONFERENCE (IEMDC), 2019, : 1641 - 1646
  • [8] A Power Hardware-in-the-Loop Testbench for Aerospace Applications
    Noon, John
    Song, He
    Wen, Bo
    Burgos, Rolando
    Cvetkovic, Igor
    Boroyevich, Dushan
    Srdic, Srdjan
    Pammer, Gernot
    [J]. 2020 THIRTY-FIFTH ANNUAL IEEE APPLIED POWER ELECTRONICS CONFERENCE AND EXPOSITION (APEC 2020), 2020, : 2884 - 2891
  • [9] Stability of a Switched Mode Power Amplifier Interface for Power Hardware-in-the-Loop
    Marks, Nathan D.
    Kong, Wang Y.
    Birt, Daniel S.
    [J]. IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, 2018, 65 (11) : 8445 - 8454
  • [10] Power Hardware-In-the-Loop Approach for Autonomous Power Generation System Analysis
    Racewicz, Szymon
    Kutt, Filip
    Sienkiewicz, Lukasz
    [J]. ENERGIES, 2022, 15 (05)