Basic Characteristic of 5-level Inverter with Different Divided DC Link Voltage

被引：0
|
作者：
Matsumoto, T. [1 ]
Akisawa, T. [1 ]
Matsuse, K. [1 ]
机构：
[1] Meiji Univ, Dept Elect Engn, Tokyo 101, Japan
来源：
2012 15TH INTERNATIONAL CONFERENCE ON ELECTRICAL MACHINES AND SYSTEMS (ICEMS 2012) | 2012年
关键词：
multi-level; harmonic; divided DC link voltage; increase output voltage level;
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
This paper report on experimental results of 5-level inverter by DC diveided link voltage. We have alreday reported that DC divided link valtage comes to be able to red use harmonic of out line voltage. So we tested whether DC divided link voltage can reduce harmonics in experimental setup. harmonics in experimental setup. This paper shows simulation results and experimental results. And we confirmed that DC divided link voltage can also apply in experimental setup.
引用
收藏
页数：4
相关论文
共 50 条
  • [41] Evaluation of Modulation Techniques for 5-Level Inverter Based on Multicarrier Level Shift PWM
    Tamasas, Mohamed
    Saleh, Mohammed
    Shaker, Mahmoud
    Hammoda, Ahmed
    2014 17TH IEEE MEDITERRANEAN ELECTROTECHNICAL CONFERENCE (MELECON), 2014, : 17 - 23
  • [42] DC-link capacitor voltage balance of NPC/H bridge five-level inverter
    Dai P.
    Zhou K.
    Gao A.-J.
    Zhu X.-W.
    Dianji yu Kongzhi Xuebao/Electric Machines and Control, 2019, 23 (03): : 42 - 50
  • [43] A Comparative Study of 5-level and 7-level Multilevel Inverter Connected to the Grid
    Yusof, Nurul Aisyah
    Sapari, Norazliani Md
    Mokhlis, Hazlie
    Selvaraj, Jeyraj
    2012 IEEE INTERNATIONAL CONFERENCE ON POWER AND ENERGY (PECON), 2012, : 542 - 547
  • [44] A New Fault Tolerant Single Phase 5-Level Inverter Topology With Capacitor Voltage Balancing For Solid State Transformer
    Saketi, Sai Krishna
    Chaturvedi, Pradyumn
    Suryawanshi, Hiralal Muralidhar
    Yadeo, Dharmendra
    Atkar, Dipesh
    45TH ANNUAL CONFERENCE OF THE IEEE INDUSTRIAL ELECTRONICS SOCIETY (IECON 2019), 2019, : 4595 - 4600
  • [45] Voltage balancing technique in a space vector modulated 5-level multiple-pole multilevel diode clamped inverter
    Raj, Pinkymol Harikrishna
    Maswood, Ali I.
    Ooi, Gabriel H. P.
    Lim, Ziyou
    IET POWER ELECTRONICS, 2015, 8 (07) : 1263 - 1272
  • [46] Single-Phase, Seven-Level Inverter with Triple Voltage Boosting and Self DC-Link Voltage Balancing
    Alsolami, Mohammed
    ARABIAN JOURNAL FOR SCIENCE AND ENGINEERING, 2024, 49 (05) : 6815 - 6830
  • [47] Simple PWM technique of capacitor voltage balance for three-level inverter with DC-link voltage sensor only
    Lai, Yen-shin
    Chou, Yi-Kai
    Pai, Sheng-Yu
    IECON 2007: 33RD ANNUAL CONFERENCE OF THE IEEE INDUSTRIAL ELECTRONICS SOCIETY, VOLS 1-3, CONFERENCE PROCEEDINGS, 2007, : 1749 - +
  • [48] Single-Phase, Seven-Level Inverter with Triple Voltage Boosting and Self DC-Link Voltage Balancing
    Mohammed Alsolami
    Arabian Journal for Science and Engineering, 2024, 49 : 6815 - 6830
  • [49] THD Improvement for a Multilevel DC-Link Inverter with Variable DC Voltage Sources
    Alhassan, Mohammad
    Singh, Santosh K.
    2022 IEEE INTERNATIONAL CONFERENCE ON POWER ELECTRONICS, DRIVES AND ENERGY SYSTEMS, PEDES, 2022,
  • [50] A 5-Level Cascaded Hybrid Multilevel Inverter for Interfacing with Renewable Energy Resources
    Khomfoi, Surin
    Aimsaard, Chatrchai
    ECTI-CON: 2009 6TH INTERNATIONAL CONFERENCE ON ELECTRICAL ENGINEERING/ELECTRONICS, COMPUTER, TELECOMMUNICATIONS AND INFORMATION TECHNOLOGY, VOLS 1 AND 2, 2009, : 255 - +
12345