Runtime Reconfigurable Bus Arbitration for Concurrent Applications on Heterogeneous MPSoC Architectures

This paper describes a runtime reconfigurable bus arbitration technique for concurrent applications on heterogeneous Multi-Processor System-on-Chip (MPSoC) architectures. Here, a hardware/software approach is introduced as part of a runtime framework that enables selecting and adapting different policies (i.e., fixed-priority, Time-Division Multiple Access (TDMA), and Round-Robin) such that the performance goals of concurrent applications can be satisfied. To evaluate the hardware cost, we provide an implementation on a Xilinx Virtex-6 FPGA and compare our proposed solution with respect to a well-known SPARC V8 architecture supporting fixed-priority arbitration. Notably, for providing the flexibility for selecting up to three different policies, our reconfigurable arbiter needs only 25% and 7% more Lookup Tables (LUTs) and slice registers, respectively. The reconfiguration overhead for switching between different policies is 56 cycles. For programming new time slots, only 28 cycles are necessary. For demonstrating the benefits of this reconfiguration framework, we have setup a mixed hard/soft real-time scenario by considering four applications with different timeliness requirements. The experimental results show that by reconfiguring the arbiter, less processing elements can be used for achieving a specific target frame rate. Moreover, by adjusting the time slots for TDMA, we can speedup a soft real-time algorithm while still satisfying the deadlines for hard real-time applications.