A Physical Model for Metal-Oxide Thin-Film Transistor Under Gate-Bias and Illumination Stress

A negative shift in the turn-on voltage of a metal-oxide thin-film transistor under negative gate-bias and illumination stress has been frequently reported. The stretched-exponential equation, predicated largely on a charge-trapping mechanism, has been commonly used to fit the time dependence of the shift. The fitting parameters, some with unsubstantiated physical origin, are extracted by curve fitting. A more physically based model is presently formulated, incorporating the photogeneration, transport, and trapping of holes. The model parameters of generation energy barrier, hole mobility, and trapping time constant are extracted from the measured gate-bias dependent turn-on voltage shift. It is theoretically deduced and experimentally verified that the degradation kinetics is either generation or transport limited. The model can be further applied to explain the attenuated shift under positive bias and illumination stress, if the screening of the electric field emanating from the gate bias is also accounted for. From the effects of asymmetric source/drain bias applied during stress, it is deduced that the trapping is localized along the length of the channel interface. The turn-on voltage of a transistor after such stress is constrained by the portion of the channel exhibiting the smallest shift.