System-level verification - A comparison of approaches

Design verification is beginning to dominate design cycle rimes as design complexity increases. As more and more electronic products have software content-and many of them large software content -software verification is often the pacing factor in completing a product. Designers are often faced with serious project delays when they wait for first silicon to begin software debugging. System-level verification addresses verification of ASIC/IC, board-level design, FPGA programming, and software with as much concurrency as possible with the goal of minimizing the project schedule. There are a variety of approaches to system-level verification depending on the verification objectives and performance requirements. This paper will describe four different approaches to system verification and the trade-offs of each approach. Examples from actual projects will be used to demonstrate the application of each approach. Recommendations for determining the best verification approach are also given.