Faster RSA encryption/decryption architecture using an efficient high speed overlay multiplier

This paper proposes the hardware implementation of RSA encryption algorithm using the recently proposed hierarchical overlay multiplier architecture. In the hierarchical overlay architecture, we have grouped 4 bits of the multiplier and multiplicand at a time and thereafter apply vertical and crosswise algorithm to decompose whole of the multiplication operation into 4x4 parallel multiply modules. The coding of the RSA is done in Verilog HDL and the FPGA synthesis is done using Xilinx libraries. The result shows that RSA hardware implemented using proposed architecture is faster than RSA hardware implemented using traditional multiplication algorithms.