A Flexible DNN Accelerator Design with Layer Pipeline for FPGAs

Deep Neural Networks (DNNs) are very effective for image recognition, object detection and tracking To meet the need of deployment of DNNs, accelerator designs have been proposed, especially for implementation on FPGAs. Layer pipeline is a new technology to improve computation efficiency by reducing latency between layers. In this paper, we propose a group-based DNN pipeline accelerator design for FPGAs. An entire DNN is partitioned into layer groups with pipeline computation within every group. A configurable logic is used to switch between groups instantaneously. Thus, our design can handle any size DNNs on a single FPGA chip. We evaluate our accelerator for Alexnet and VGG16 on a Xilinx ZC706 board. Our experimental results show that we can increase the throughput by 19% and 42% when compared with layer-based accelerators in [1] and [16].