A Cost-Effective Scheme for Network-on-Chip Router and Interconnect Testing

被引:9
|
作者
Xiang, Dong [1 ]
机构
[1] Tsinghua Univ, Sch Software, Beijing 100084, Peoples R China
关键词
COMMUNICATION; DESIGN; NOCS;
D O I
10.1109/ATS.2013.46
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
3-D technology for networks-on-chip (NoCs) becomes attractive. It is important to present an effective scheme for 3-D stacked NoC router and interconnect testing. A new approach to testing of NoC routers is proposed by classifying the routers. Routers with different input/output ports fall into different classes. Routers of the same class are identical, whose tests are the same. A new unicast-based multicast scheme is proposed for the identical routers. A new test application scheme is proposed for interconnect testing. Sufficient experimental results are presented.
引用
收藏
页码:207 / 212
页数:6
相关论文
共 50 条
  • [31] An Asynchronous Network-on-Chip Router with Low Standby Power
    Elshennawy, Amr
    Khatri, Sunil P.
    [J]. 2014 32ND IEEE INTERNATIONAL CONFERENCE ON COMPUTER DESIGN (ICCD), 2014, : 394 - 399
  • [32] A load balancing bufferless deflection router for network-on-chip
    周小锋
    朱樟明
    周端
    [J]. Journal of Semiconductors, 2016, (07) : 108 - 115
  • [33] Multicast parallel pipeline router architecture for network-on-chip
    Samman, Faizal A.
    Hollstein, Thomas
    Glesner, Manfred
    [J]. 2008 DESIGN, AUTOMATION AND TEST IN EUROPE, VOLS 1-3, 2008, : 1200 - 1205
  • [34] A novel technique for flit traversal in network-on-chip router
    Monika Katta
    T. K. Ramesh
    Juha Plosila
    [J]. Computing, 2023, 105 : 2647 - 2673
  • [35] Tackling Permanent Faults in the Network-on-Chip Router Pipeline
    Poluri, Pavan
    Louri, Ahmed
    [J]. 2013 25TH INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE AND HIGH PERFORMANCE COMPUTING (SBAC-PAD), 2013, : 49 - 56
  • [36] Centralized Priority Management Allocation for Network-on-Chip Router
    Yan, Pengzhan
    Sridhar, Ramalingam
    [J]. 2018 31ST IEEE INTERNATIONAL SYSTEM-ON-CHIP CONFERENCE (SOCC), 2018, : 290 - 295
  • [37] Analyzing the Error Propagation in a Parameterizable Network-on-Chip Router
    de Melo, Douglas Rossi
    Zeferino, Cesar Albenes
    Dilillo, Luigi
    Bezerra, Eduardo Augusto
    [J]. 2019 20TH IEEE LATIN AMERICAN TEST SYMPOSIUM (LATS), 2019,
  • [38] Design and implementation of congestion aware router for network-on-chip
    Balakrishnan, Melvin T.
    Venkatesh, T. G.
    Bhaskar, A. Vijaya
    [J]. INTEGRATION-THE VLSI JOURNAL, 2023, 88 : 43 - 57
  • [39] Roundabout: a Network-on-Chip Router with Adaptive Buffer Sharing
    Effiong, Charles
    Sassatelli, Gilles
    Gamatie, Abdoulaye
    [J]. 2017 IEEE 15TH INTERNATIONAL NEW CIRCUITS AND SYSTEMS CONFERENCE (NEWCAS), 2017, : 65 - 68
  • [40] A Spare Router based Reliable Network-on-Chip Design
    Chatterjee, Navonil
    Chattopadhyay, Santanu
    Manna, Kanchan
    [J]. 2014 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), 2014, : 1957 - 1960