An improved low-cost 6.4 Gbps wafer-level tester

This paper describes an economical approach to highspeed testing of high-density wafer-level packaged logic devices. The solution assumes that the devices to be tested have built-in self-test features, thereby reducing the complexity of functional testing required. This also reduces the need for expensive automated test equipment (ATE). A stand alone miniature tester is developed and connected to the top of a wafer probe card with multiple high-speed (up to 6.4 Gbps) signals. Off the shel components are used in order to keep costs low. However its performance in some aspects exceeds that of traditional ATE. Measurements illustrate the tester generating 6.4 Gbps signals with a +25ps timing accuracy. The generated signals exhibit low jitter similar to 40ps and have low rise times on the order of 50-70ps.