Novel VLSI architecture of motion estimation for H.264 standard

被引：0

作者：

Li, X ^{[1
]}

Chopra, R ^{[1
]}

Hsu, KW ^{[1
]}

机构：

[1] Rochester Inst Technol, Rochester, NY 14623 USA

来源：

IEEE INTERNATIONAL SOC CONFERENCE, PROCEEDINGS | 2005年

关键词：

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

A novel architecture to achieve real-time motion estimation compensation encoding for H.264 ITU Video compression standard is presented. A full-search block matching algorithm has been adapted to a pipelined data flow to enable parallel processing of variable block sized block matching and fractional pixel motion vector generation. The SOC is designed with TSMC 0.18um technology using VHDL and optimized to achieve a 125 MHz clock speed to make real-time processing possible.

引用

页码：117 / 118

页数：2

共 50 条

[1] High data reuse VLSI architecture for H.264 motion estimation
Zheng Zhaoqing
Sang Hongshi
Huang Weifeng
Shen Xubang
[J]. 2006 10TH INTERNATIONAL CONFERENCE ON COMMUNICATION TECHNOLOGY, VOLS 1 AND 2, PROCEEDINGS, 2006, : 1245 - +
[2] New VLSI architecture for fractional motion estimation of H.264/AVC
Zheng, Zhao-Qing
Sang, Hong-Shi
Lai, Xiao-Ling
Shen, Xu-Bang
[J]. Jisuanji Xuebao/Chinese Journal of Computers, 2007, 30 (12): : 2101 - 2108
[3] VLSI Architecture Design of Fractional Motion Estimation for H.264/AVC
Yi-Hau Chen
Tung-Chien Chen
Shao-Yi Chien
Yu-Wen Huang
Liang-Gee Chen
[J]. Journal of Signal Processing Systems, 2008, 53 : 335 - 347
[4] VLSI Architecture Design of Fractional Motion Estimation for H.264/AVC
Chen, Yi-Hau
Chen, Tung-Chien
Chien, Shao-Yi
Huang, Yu-Wen
Chen, Liang-Gee
[J]. JOURNAL OF SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY, 2008, 53 (03): : 335 - 347
[5] An Efficient VLSI Architecture of Fractional Motion Estimation in H.264 for HDTV
Ruiz, G. A.
Michell, J. A.
[J]. JOURNAL OF SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY, 2011, 62 (03): : 443 - 457
[6] An Efficient VLSI Architecture of Fractional Motion Estimation in H.264 for HDTV
G. A. Ruiz
J. A. Michell
[J]. Journal of Signal Processing Systems, 2011, 62 : 443 - 457
[7] An efficient VLSI architecture for H.264 variable block size motion estimation
Ou, CM
Le, CF
Hwang, WJ
[J]. IEEE TRANSACTIONS ON CONSUMER ELECTRONICS, 2005, 51 (04) : 1291 - 1299
[8] High performance VLSI architecture of fractional motion estimation in H.264 for HDTV
Yang, Changqi
Goto, Satoshi
Ikenaga, Takeshi
[J]. 2006 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-11, PROCEEDINGS, 2006, : 2605 - +
[9] A Complete H.264 Motion Estimation Architecture
Siqueira, Hadley
Lopes, Alba
Marinho, Victor
Correa, Edgard
[J]. 2012 BRAZILIAN SYMPOSIUM ON COMPUTING SYSTEM ENGINEERING (SBESC 2012), 2012, : 111 - 114
[10] Fractional full-search motion estimation VLSI architecture for H.264/AVC
Ou, Chien-Min
Roan, Huang-Chun
Hwang, Wen-Jyi
[J]. ADVANCES IN IMAGE AND VIDEO TECHNOLOGY, PROCEEDINGS, 2006, 4319 : 861 - +

← 1 2 3 4 5 →