Testing Xilinx XC4000 configurable logic blocks with carry logic modules

被引：3

作者：

Sun, XL ^{[1
]}

Xu, J ^{[1
]}

Trouborst, P ^{[1
]}

机构：

[1] Univ Alberta, Dept Elect & Comp Engn, Edmonton, AB T6G 2G7, Canada

来源：

2001 IEEE INTERNATIONAL SYMPOSIUM ON DEFECT AND FAULT TOLERANCE IN VLSI SYSTEMS, PROCEEDINGS | 2001年

关键词：

D O I：

10.1109/DFTVS.2001.966774

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper presents a novel built-in self-rest (BIST) scheme for configurable logic blocks (CLBs) of Xilinx XC4000 field programmable gate arrays (FPGAs). The test of the dedicated carry logic module (CLM) within a CLB is included for the first time, A minimum of eight CLB rest configurations is given. A centralized BIST architecture supports the single stuck-at fault rest of the CLM and the whole CLB. The scheme is also capable of locating any faulty CLBs with the maximum diagnostic resolution, two adjacent CLBs.

引用

页码：221 / 229

页数：9

共 30 条

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